The following example shows how STA checks setup and hold constraints for a flip-flop:įor this example, assume that the flip-flops are defined in the logic library to have a minimum setup time of 1.0 time units and a minimum hold time of 0.0 time units. This constraint enforces a minimum delay on the data path relative to the clock edge. A hold constraint specifies how much time is necessary for data to be stable at the input of a sequential device after the clock edge that captures the data in the device.This constraint enforces a maximum delay on the data path relative to the clock edge. A setup constraint specifies how much time is necessary for data to be available at the input of a sequential device before the clock edge that captures the data in the device.STA then checks for violations of timing constraints, such as setup and hold constraints: This delay is caused by the parasitic capacitance of the interconnection between the two cells, combined with net resistance and the limited drive strength of the cell driving the net. Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path. From these table entries, the tool calculates each cell delay. Typically, a delay table lists the amount of delay as a function of one or more variables, such as input transition time and output load capacitance. In the absence of back-annotated delay information from an SDF file, the tool calculates the cell delay from delay tables provided in the logic library for the cell. The total delay of a path is the sum of all cell and net delays in the path.Ĭell delay is the amount of delay from input to output of a logic gate in a path. After breaking down a design into a set of timing paths, an STA tool calculates the delay along each path.
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